1. Field of the Invention
The present invention relates to a method for fabricating a semiconductor device, in particular to a method for fabricating the semiconductor device which comprises transistors with an elevated source/drain structure and transistors with a normal source/drain structure.
2. Description of the Background Art
Many semiconductor manufacturers have made great efforts to improve a density of semiconductor devices. In recent years, in a field of the semiconductor devices, particularly to memory devices, transistors of a memory cell unit are designed to operate at about 1.8V of low voltage and transistors of an input/output circuit unit are designed to operate at 3.3V or 5V higher than a operating voltage of memory cell unit. Thus, a thickness of a gate insulation layer of transistors in a memory cell unit is different from a thickness of a gate insulation layer of transistors in an input/output circuit unit.
A method for fabricating devices having different thickness of gate insulation layers in one semiconductor substrate will now be described.
As shown in FIG. 1A, a thick oxide layer 101 is formed on the upper surface of a substrate 100.
Then a photoresist layer 102 is formed on all upper surface of the thick oxide layer 101 and patterned by photo lithography process, thereby remaining photoresist layer 102 only on the thick oxide layer 101 of an input/output circuit unit "A" as shown in FIG. 1B. Then, thick oxide layer 101 of a memory cell unit "B" is etched away using the photoresist layer 102 as a mask.
As shown in FIG. 1C, after removing the photoresist layer 102, a thin oxide layer 103 is formed on the upper surface of the semiconductor substrate 100 of the memory cell unit "B".
As shown in FIG. 1D, gate electrodes 104 are formed on the each upper surface of the thick oxide layer 101 and thin oxide layer 103. Then lightly doped impurity regions 105 are formed in the semiconductor substrate 100 by implanting impurity ions at both sides of each gate electrode 104.
As shown in FIG. 1E, sidewall spacers 106 are formed on both sides of each gate electrode 104. Source/drain regions 107 are formed by implanting the impurity ions into the semiconductor substrate 100 at the both sides of the sidewall spacers 106. After that, a silicide layer 108 is formed on the upper surface of the source/drain regions 107.
However, the above-described conventional method for fabricating the semiconductor device has the below problems. In the transistors of the memory cell unit, many problems such as a short channel effect may occur because a length of the channel is very short, particularly a punch-through phenomenon, is serious. In addition, an increase of junction leakage current is a problem when the silicide layer is formed on the upper surface of the source/drain because a depth of the source/drain junction is decreased.